The present invention relates to multi-core processors, and, in particular, to systems and methods for maximizing performance of multi-core processors in power-constrained environments.
Modern computer processors typically include multiple central processing unit (“CPU”) cores for executing one or more applications comprised of instruction code. Such multi-core processors may contain anywhere from a few cores to a large number of cores depending on the architecture and the technology process used.
Each core in a multi-core processor is typically capable of reading and executing a sequence of instruction code known as a thread. Within each thread, a core may also execute instructions in parallel and/or out of order to maximize performance to the extent that instruction interdependencies allow. This is known as instruction level parallelism (“ILP”). In general, the more resources a core has the higher the performance may be for applications with code presenting high instruction level parallelism.
Additionally, multiple cores may be used to each execute multiple threads of an application at the same time. This is known as thread level parallelism (“TLP”). In general, the more cores a multi-core processor has the more threads it may concurrently execute for applications presenting high thread level parallelism.
Multi-core processors typically operate at a particular voltage and frequency. In general, higher processor performance may be achieved by operating the processor at a higher frequency, and higher frequencies typically require operating the processor at a higher voltage. In other words, processor performance is typically related to frequency and, proportionally, to voltage.
Multi-core processors also typically operate in power-constrained environments with a maximum power budget. Consequently, processor performance, as determined by the maximum operating voltage and frequency, is typically limited by a predetermined maximum amount of power. In such cases, raising the voltage and frequency any further would often result in exceeding the maximum amount of power.
In addition, fully operating all cores available in a multi-core processor, and all resources available per core, such as an instruction queue, a physical register file, a re-order buffer, a load-store-queue, caches and execution units, may result in exceeding the maximum amount of power. If the maximum amount of power is exceeded, the processor may exhibit failures and/or become susceptible to damage.
Dynamically scaling processor voltage and frequency is a known method for providing power management for processors operating in such power-constrained environments. Under such voltage/frequency scaling methods, voltage and frequency may each be dynamically reduced at particular times to conserve power. This may, in turn, allow a processor to increase the number of operating cores, thereby improving the performance of applications exhibiting high thread level parallelism in power-constrained environments.
However, as the ability for voltage and frequency scaling lessens due to decreases in nominal core operating voltages and increases in manufacturing process variations, meeting a maximum power budget via voltage and frequency scaling becomes far more challenging and less feasible.